Art
Altar Ergo Prints
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Original illustration and fine art prints for conscious spaces — each piece a study in narrative and observation. Signature works, limited editions, and commissions.
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New Delhi
Strategy at the intersection of technology,
creative enterprise, and speed.
About
I spent five years as a Senior Associate in Bain & Company's Technology, Media & Telecommunications practice, advising governments and global corporations on semiconductor strategy, telecom transformation, and technology market entry. My work spanned South Korea, the European Union, the United States, Southeast Asia, and India — from chip architecture and foundry investment to national semiconductor ecosystem design.
I am an engineer who became a strategist and an artist who thinks in systems. That combination — technical fluency, commercial rigour, and creative intelligence — is what I bring to every engagement. I am particularly drawn to the problems that live at the edges of disciplines: where policy meets market structure, where precision engineering meets visual communication, where analytical frameworks meet human stories.
Alongside my advisory work, I run Altar Ergo Prints, a fine art print practice rooted in original illustration and fine art. I am developing ventures in the motorsport ecosystem — an industry I believe is undergoing a structural commercial transformation — and I collaborate selectively with publishers, galleries, and technology organisations on creative and strategic projects.
I am based in New Delhi and work internationally, with particular focus on the India-Europe technology corridor.
What I do
Semiconductor market intelligence, government advisory, market entry strategy, and competitive analysis for foreign organisations navigating India's technology landscape. Formerly Bain & Company TMT practice.
Strategic counsel for European, Nordic, and East Asian organisations entering or deepening their India presence in semiconductors and digital infrastructure. Market landscape, policy interpretation, and commercial structuring — translating a complex environment into clear decisions.
Commercial strategy and venture development at the intersection of motorsport, automotive technology, and digital platforms. Building for an ecosystem undergoing structural transformation.
Original illustration and fine art prints under the Altar Ergo label. Work that lives at the edge of narrative and observation, created by hand in deep detail to add symphonies to spaces.
Visit Altar Ergo →Background
Bain & Company
Senior Associate · TMT Practice · 2020–2025
End-to-end delivery of semiconductor and technology strategy engagements for governments and corporations across Korea, the EU, the US, Southeast Asia, and India — spanning portfolio strategy, market entry, and national ecosystem development. Work that ranged from chip architecture and foundry investment analysis to advising a government on its semiconductor roadmap.
NITI Aayog
Science & Technology Intern · 2018
Co-authored India's National Strategy for Artificial Intelligence — the foundational policy document for India's AI ambitions. Launched the Global Mobility Hack 'Move Hack 2018' as part of an eight-member team, working at the intersection of technology policy and urban mobility.
NSIT Debating Society
Vice President · NSIT MUN, Director General
Outstanding Delegate at Harvard National MUN 2017, among 3,000+ delegates from 75 countries. Led a 40-member team to organise NSIT's Model UN. Trained 25 debaters resulting in 80+ state-level awards and 5 international recognitions.
NSIT, Delhi University
B.E. Electronics & Communications Engineering · 2020
Engineering foundation in electronics, communications systems, and signal processing — the technical layer beneath a career of strategic work in semiconductors and technology.
Thinking
Analytical writing on semiconductors, technology policy, and the India-Europe strategic corridor. Notes on motorsport, design, and the business of creative enterprise.
When India launched the Semiconductor Mission in December 2021 with a ₹76,000 crore outlay, the scheme was met with reasonable scepticism. India had announced chip ambitions before, and the incentive structure — initially offering varying levels of fiscal support before being unified to a flat 50% of project cost in the September 2022 revision — was generous but unproven. Four years on, the more interesting question is not whether the money was committed, but what shape the resulting ecosystem has taken, and where the foreign capital actually went.
The pattern is revealing. The first wave of approvals clustered heavily around ATMP and OSAT — assembly, testing, and packaging — rather than front-end fabrication. Micron's Sanand facility, now operational, anchored this trend; Kaynes Semicon reached commercial production in early 2026, roughly fourteen months after breaking ground. This is not the failure some read it as. Packaging is the pragmatic first rung: lower capital intensity, faster payback, and a genuine integration point into global supply chains. The Tata-PSMC fab at Dholera — the one true large-scale fabrication play, at a 28nm node — remains the harder, slower, more capital-hungry bet, and its progress is the real test of the programme.
For foreign investors, the most important structural detail is the technology-partner requirement. ISM's appraisal process has consistently rejected applications lacking a credible foundry partnership — a foreign firm cannot simply propose in-house capability. This is why the meaningful foreign participation has come as partnerships: PSMC with Tata, Renesas with CG Power, and more recently equipment and materials players like ASML establishing India footprints. ISM 2.0, announced in Budget 2026, tacitly acknowledges the gap ISM 1.0 left — equipment, materials, speciality chemicals, and design IP all remain overwhelmingly imported. That is precisely where the next decade of foreign entry will be negotiated, and where the incentive structure is now being pointed.
The story most people still tell about the AI chip shortage — packed fabs, scarce wafers, allocation queues at the leading edge — describes a constraint that has largely moved on. By 2026, the binding limit on AI hardware is no longer wafer starts. It is advanced packaging, and specifically TSMC's CoWoS capacity, which has been reported sold out through the year with lead times stretching past a year. A fabricated die is not a finished accelerator; it is silicon waiting for a packaging process that is scarcer than the silicon itself.
This shift has quietly reordered the competitive landscape. When a single customer can lock up the majority of a foundry's advanced-packaging allocation, the ceiling on everyone else's AI roadmap is set not by their own design cadence but by their place in someone else's queue. High-bandwidth memory compounds the squeeze — HBM supply is dominated by a small number of Korean and US players, and near-term inventory has been repeatedly described as fully committed. The constraint is now three-dimensional: wafer starts, packaging slots, and memory allocation must all be secured at once, and of the three, packaging is the one that bites.
The strategic consequence is that the hyperscalers' move into custom silicon — TPUs, Trainium, in-house accelerators — does not escape the bottleneck so much as relocate demand within it. Custom chips still compete for the same CoWoS and HBM capacity. For anyone modelling the AI supply chain, this is the point that matters: capacity expansions at the packaging layer, not headline wafer numbers, are the leading indicator of when the constraint eases. Most projections put meaningful relief no earlier than 2027, and only if expansion holds pace with a demand curve that has repeatedly outrun it.
On June 4th, the EU Delegation to India and MeitY convened the first EU-India Tech Business Forum in New Delhi, bringing together over 100 European and Indian technology companies under the Trade and Technology Council framework. Eight European ambassadors attended. The subject matter — semiconductors, AI, cybersecurity, data governance — was not new. What was new was the format: industry, for the first time since the TTC's founding in 2022, sitting directly at the table with policymakers.
That shift matters more than any single outcome from the day. TTC Working Group 1 has spent three years building the scaffolding — the EU-India Free Trade Agreement, the Advanced Electronic Signatures Administrative Arrangement, a European Legal Gateway Office to ease mobility of Indian ICT professionals into the EU. The June forum signals that phase is ending and an execution phase is beginning, one where individual companies — not just ministries — need people who can translate policy architecture into commercial action.
For a European semiconductor or industrial technology firm evaluating India right now, the practical question is no longer "should we enter" but "which mechanism gets us there fastest" — FTA tariff provisions, TTC-aligned joint R&D calls, or direct state-level investment incentives under the India Semiconductor Mission. Each pathway has a different timeline, a different set of gatekeepers, and a different risk profile. Getting that sequencing right is where most market entries either compound or stall — and it is the layer of work that sits just beneath the diplomatic headlines.
Art
Store opening soon
Original illustration and fine art prints for conscious spaces — each piece a study in narrative and observation. Signature works, limited editions, and commissions.
Preview the collection →
Contact
I am open to strategic advisory engagements, collaborative ventures, speaking invitations, and creative partnerships. Particularly interested in European and Nordic organisations navigating India's technology and policy landscape.